Chickens.
Although I was unable to physically attend the Open Compute Project (OCP) Summit, I did get information on several storage and memory related developments at the show. Let’s look at these developments in chipsets, enhanced Ethernet systems, device-level security auditing, data center SSDs and SSDs, and domain-specific CPU controllers.
The OCP Foundation and JEDEC Solid State Technology Association reported joint development for automated System in Package (SiP) design and construction using Chiplets. This included a Chiplet Description Schema (CDXML) specification that enables standardized descriptions of Chiplet parts for use with modern EDA tools and allows chiplet builders to provide electronically readable descriptions to their customers. CDML is being integrated into JEDEC JEP30. OCP grants a free, non-exclusive right to incorporate CDXML into JEP30.
Electronically readable descriptions of chiplets include: thermal, physical/mechanical, behavioral, power/power and signal integrity, electrical testing, and safety information. These new standards should help establish an Open Chiplet economy. The goal is to build an Open Chiplet economy as illustrated below.
OCP and JEDEC chipset ecosystem
The OCP Foundation and the Ultra Ethernet Consortium announced an alliance to help provide data center equipment optimized for artificial intelligence (AI) and high-performance computing (HPC) applications. This includes addressing the memory size and back-end structure issues of AI clusters posed by large language models (LLM). This will help accelerate the integration of UCE-inspired Ethernet enhancements into complete systems. This will enable OCP to support its multi-vendor supply chain to deliver these enhanced Ethernet systems.
This allows the integration of specialized silicon systems developed using Chiplets and large memory pools created with CXL and various memory devices. The OCP Foundation also announced its Security Appraisal Framework and Enablement (SAFE) program to enable standardized device-specific security auditing. This aims to reduce costs, decrease redundancy and provide common security compliance for device customers.
Kioxia also participated in the OCP Summit highlighting its data center and enterprise SSD portfolio. In particular, the company talked about its XD7P data center NVMe SSDs, as shown below, as well as Kioxia’s LD2-L NVMe SSD (in a 9.5mm EDSFF E1.L form factor) and CD8P Data Center PCIe 5.0 NVMe SSD (in EDSFF E3.5 format). and 2.5-inch (U.2) 15mm-thick form factors).
KIOXIA XD7P NVMe Data Center SSD
These products also work with Software-Enabled Flash (SEF) data management to control data placement, provide workload isolation, reduce write amplification, and optimize latency. This enables advanced queuing, I/O prioritization, and custom protocols with open source APIs and SDKs.
Phison demonstrated high-speed signal-enhanced IC products at the OCP Summit to expand its PCIe 5.0 and CXL 2.0 ecosystem for AI-driven data centers. These developments include PCIe 5.0 and CXL 2.0 compliant data signal conditioning IC products. These products are intended for NAND flash products for AI applications, including machine learning (ML). The company currently has PCIe 4.0 and 5.0 products in mass production and PCIe 6.0 products in design.
Phison’s PS7201 and PS7202 retiming solutions are designed to meet the growing demand for data performance and follow industry standard retiming footprints. In addition to working with NAND flash, these solutions work with acceleration technologies such as GPU, CPU, FPGA, ASIC and DPU. They increase 5ns latency with pin-to-pin compatibility with competitive products. These products are PCI-SIG certified. Phison also offers the PHiTUNE auto-tuning tool for its retimers. This tool allows development engineers to collect signal data and determine the best parameters for signal optimization in 30 minutes.
The OCP Summit introduced new Chiplet enablement, advanced Ethernet, and device security auditing. Kioxia showed off its data center SSD products and Phison announced new controller technology for PCIe 5.0 and CXL 2.0 devices.